Zoho bets on fabless chip design after shelving a $700M fab. Sridhar Vembu reveals how AI EDA cuts tape-out cycles 10x for sovereign Netrasemi 12nm edge silicon.
Silicon & Datacenter Chips
39 Articles in this Category
Deep architectural analysis of frontier AI silicon: Nvidia Blackwell/Rubin, Google TPU, Groq LPUs, and packaging technologies.
Xiaomi streamed its $3.5M real-time RL run for MiMo-V2.6. An architectural audit of live cluster telemetry, fatal OOM restarts, GRPO mechanics, and benchmark tops.
Constellation targets a 2027 restart of Three Mile Island Unit 1 under a Microsoft power agreement. The reactor has not been shown to have reopened.
Anthropic released Claude Opus 5.5 on September 22, 2026: 66.4% Terminal-Bench, 54.4% FrontierCode, matching Fable 5.1 at $4/$20 with 60% cheaper prompt caching.
Executive Briefing Donald Trump’s warning that “whoever wins AI wins everything” was treated in Washington as an…
Alibaba unveiled 10T Qwen scaling, the 500k-node Zhenwu V900 chip, and a 20GW grid plan. Here is our forensic systems audit of the domestic ASI sprint.
DeepSeek is training an 8-trillion-parameter MoE model on 160,000 Huawei Ascend 950DT chips. CEO Liang Wenfeng told investors the domestic chip bet “has to work.”
Applied Materials commits $5B as the Tata Dholera Fab enters cleanroom fit-out for Dec 2026 trial runs. We audit India’s 28nm equipment and supply chain.
Goldman Sachs identifies 42 Indian AI Enabler stocks up 60% YTD vs Nifty -12%. Deep-dive: exact order books, sector layer performance (40-80%), government policy stack, and structural vulnerabilities.
On September 17, 2026, Z.ai (Zhipu AI) revealed the first empirical, production-grade milestone of Recursive Self-Improvement (RSI):…